A SRAM memory cell that is a semiconductor storage element includes a basic structure described below.
As shown in a circuit diagram in FIG. 1, the SRAM memory cell is composed of a flip flop circuit as an information accumulating section, and a pair of access transistors A1 and A2 that controls the electric conduction between the flip flop circuit and data lines (bit lines BL1 and BL2) through which information is written and read. The flip flop circuit is composed of, for example, a pair of CMOS inverters. Each of the CMOS inverters is composed of one driving transistor D1 (D2) and one load transistor L1 (L2).
One of a source area and a drain area of the access transistor A1 (A2) is connected to drains of a load transistor L1 (L2) and a driving transistor D1 (D2). The other of the source area and drain area of the access transistor A1 (A2) is connected to the bit line BL1 (BL2). Furthermore, the paired access transistors A1 and A2 each constitute a part of a word line WL and are connected together.
Gates of the driving transistor D1 and load transistor L1 constituting one of the CMOS inverters are connected to drains (accumulation nodes N2) of the driving transistor D2 and load transistor L2 constituting the other CMOS inverter. Furthermore, gates of the driving transistor D2 and load transistor L2 constituting the latter CMOS inverter are connected to the drains (accumulation nodes N1) of the driving transistor D1 and load transistor L1 constituting the former CMOS inverter. Thus, between the paired CMOS inverters, the I/O section of one of the CMOS inverters and the gate of the other CMOS inverter are cross-coupled together via a pair of wires I1 and I2 called local wires.
A reference voltage (Vss, for example, GND) is supplied to source areas of the driving transistors D1 and D2. A power supply voltage (VDD) is supplied to source areas of the load transistors L1 and L2.
The SRAM cell described above has excellent element characteristics; the SRAM cell is resistant to noise and requires only low power consumption during standby. However, the SRAM cell requires six transistors for each memory cell, a large number of wires, and separation of p-type MOS elements from n-type MOS elements in the same cell. Thus, the SRAM cell is disadvantageously likely to have a large cell area. Furthermore, with the conventional SRAM cell, stored data may be destroyed during a read operation owing to an increased variation in transistor characteristics resulting from miniaturization of the transistors. In the conventional SRAM cell, the word line WL is set to a high level to energize the access transistors A1 and A2; accordingly the accumulation nodes N1 and N2 are connected to the bit lines BL1 and BL2, respectively, so that the levels of the accumulation nodes N1 and N2 change to the respective bit line levels. For example, if the storage in the accumulation node N1 is at a low level, although the bit line BL slightly raises the level of the accumulation node N1, the driving transistor D1 is on and the potential is lowered. However, if the increased potential exceeds the threshold level of the opposite driving transistor D2, the driving transistor D2 is turned on to lower the level of the accumulation node N2 and to reduce an on current for the driving transistor D1. Thus, the level of the accumulation node N1 further rises to destroy the stored data. In general, for the SRAM cell, a static noise margin (SNM) is used as an indicator for measuring the stability of data retention observed when the SRAM cell is accessed. When the SNM is higher than 0 V, a normal read operation is performed. When the SNM is lower than 0 V, during the read operation, the stored data is overwritten with inverted data and thus destroyed.
On the other hand, as a kind of MIS field effect transistor (hereinafter referred to as an “FET”), what is called an FIN FET has been proposed. The FIN FET includes a semiconductor portion shaped like a rectangular parallelepiped and projecting perpendicularly to a substrate plane, and a gate electrode extending from one side surface of the rectangular parallelepiped-shaped semiconductor portion to the opposite surface across a top surface of the portion so as to stride it. A gate insulating film is interposed between the rectangular parallelepiped-shaped semiconductor portion and the gate electrode. Channels are formed mainly along the opposite side surfaces of the rectangular parallelepiped-shaped semiconductor portion. In the FIN FET, channel width is perpendicular to the substrate plane. This is advantageous for miniaturization and advantageously improves various characteristics, for example, improves cutoff characteristic and carrier mobility and reduces a short channel effect and punch-through.
As such an FIN FET, Patent Document 1 (Japanese Patent Laid-Open No. 64-8670) discloses a MOS field effect transistor characterized by including a semiconductor portion which includes a source area, a drain area, and a channel area and which is shaped like a rectangular parallelepiped having a side surface almost perpendicular to the plane of a wafer substrate, the rectangular parallelepiped-shaped semiconductor portion having a height greater than the width thereof, the MOS field effect transistor further including a gate electrode extending perpendicularly to the plane of the wafer substrate.
Patent Document 1 illustrates a form in which the rectangular parallelepiped-shaped semiconductor portion partly constitutes a part of the silicon wafer substrate and a form in which the rectangular parallelepiped-shaped semiconductor portion partly constitutes a part of a single-crystal silicon layer in an SOI (Silicon On Insulator) substrate. The former form is shown in FIG. 2(a), and the latter form is shown in FIG. 2(b).
In the form shown in FIG. 2(a), a part of a silicon wafer substrate 101 constitutes a rectangular parallelepiped-shaped portion 103. A gate electrode 105 extends from one side to the other side of the rectangular parallelepiped-shaped portion 103 across the top thereof. Areas of the rectangular parallelepiped-shaped portion 103 which correspond to the opposite sides of the gate electrode form a source area and a drain area. A channel is formed under an insulating film 104 located under the gate electrode. Channel width is equal to twice as large as the height h of the rectangular parallelepiped-shaped portion 103. Gate length corresponds to the width L of the gate electrode 105. The rectangular parallelepiped-shaped portion 103 is formed by forming a groove in the silicon wafer substrate 101 by means of anisotropic etching so as to leave a part of the silicon wafer substrate 101 inside the groove unprocessed. Furthermore, the gate electrode 105 is provided on an insulating film 102 left in the groove, so as to extend across the rectangular parallelepiped-shaped portion 103.
In the form shown in FIG. 2(b), an SOI substrate is provided which is made up of a silicon wafer substrate 111, an insulating layer 112, and a silicon single-crystal layer. The silicon single-crystal layer is patterned to form a rectangular parallelepiped-shaped portion 113. A gate electrode 115 is provided on the exposed insulating layer 112 so as to extend across the rectangular parallelepiped-shaped portion 113. Areas of the rectangular parallelepiped-shaped portion 113 which correspond to the opposite sides of the gate electrode form a source area and a drain area. A channel is formed under an insulating film 114 located under the gate electrode. The channel width is equal to the sum of double the height a of the rectangular parallelepiped-shaped portion 113 and the width b thereof. The gate length corresponds to the width L of the gate electrode 115.
On the other hand, Patent Document 2 (Japanese Patent Laid-Open No. 2002-118255) discloses an FIN FET including a plurality of rectangular parallelepiped-shaped semiconductor portions (protruding semiconductor layers 213), for example, as shown in FIGS. 3(a) to 3(c). FIG. 3(b) is a sectional view taken along a line B-B in FIG. 3(a). FIG. 2(c) is a sectional view taken along line C-C in FIG. 3(a). The FIN FET includes a plurality of protruding semiconductor layers 213 composed of parts of a well layer 211 in a silicon substrate 210 and arranged parallel to one another. The FIN FET also includes a gate electrode 216 extending across central portions of the protruding semiconductor layers. The gate electrode 216 is formed so as to extend from a top surface of an insulating layer 214 along side surfaces of the protruding semiconductor layers 213. An insulating film 218 is interposed between each of the protruding semiconductor layers and the gate electrode. A channel 215 is formed in a part of the protruding semiconductor layer which is located under the gate electrode. Furthermore, a source/drain area 217 is formed in each of the protruding semiconductor layers. A high-concentration impurity layer (punch-through stopper layer) is provided in an area 212 under the source/drain area 217. Upper layer wires 229 and 230 are provided via an inter-layer insulating film 226 and connected to the source/drain area 207 and the gate electrode 216 by contact plugs 228. Patent Document 2 describes that this structure enables the side surfaces of the protruding semiconductor layer to be used as the channel width, allowing a reduction in planar area compared to conventional planar FETs.
In recent years, attempts have been made to apply this FIN FET to the SRAM. For example, Patent Document 3 (Japanese Patent Laid-Open No. 2-263473) describes that the FIN FET is applied to some of the transistors (which use word lines as gates) in a SRAM memory cell. Furthermore, Non-patent Document 1 (Fu-Liang Yang et al, IEDM (International Electron Devices Meeting), 2003, p. 627 to 630) shows the applicability of the FIN FET to the SRAM. Non-patent Document 2 (T. Park et al, IEDM, 2003, p. 27 to 30) and Non-patent Document 3 (Jeong-Hwan Yang et al, IEDM, 2003, p. 23 to 26) describe examples in which the FIN FET is applied to the SRAM.
The FIN FET has a higher ratio of on current to off current than conventional bulk transistors. Thus, SNM can be slightly improved by applying the FIN FET to the SRAM. However, if transistors are further miniaturized, then even with the FIN FET, it is very difficult for the six-transistor configuration of the conventional SRAM to prevent the SNM from disadvantageously becoming lower than 0 V. This may limit miniaturization.